1. Field of the Invention
The present invention relates to a dead-time locking circuit, and more particularly, to a dead-time locking circuit applied to the class D amplifier.
2. Description of the Prior Art
The control of dead-time is vital for class D amplifiers. The conventional dead-time generator merely comprises logic gates so that the period of the dead-time cannot be locked. Hence the dead-time is easily affected by the process/temperature variation. If the generated dead-time is too short, the power transistors at the output stage of the class D amplifier are possibly turned on at the same time, which generates a large transient current and excessive heat, further causing the damage of the power transistors. Otherwise, if the dead-time is too long, the distortion of the output signal is increased. Furthermore, the over-long or over-short dead-times decrease the output efficiency of the class D amplifier. Therefore, in the design of the class D amplifier, the period of the dead-time is required to be designed appropriately and with low variation. In this way, the distortion of the output signal will not be deteriorated and the class D amplifier will not be damaged by being overheated.